This is an update to previous post. If you want to wait for no of clocks in TB/sequence rather than giving delay, which can be done by events as shown below, but not recommended. Recommended solution is given below that.
we can use the same uvm_event.
we can get the event with the help of uvm_event_pool, the sharing of the event happens with respect to the name with which you have set your clock event.
Please find the code snippet below.
example:
we can use the same uvm_event.
we can get the event with the help of uvm_event_pool, the sharing of the event happens with respect to the name with which you have set your clock event.
Please find the code snippet below.
example:
class my_sequence extends uvm_sequence; //factory registration //other stuff uvm_event_pool my_event_pool; uvm_event clk_event; . . . clk_event = new(); my_event_pool = uvm_event_pool::get_global_pool(); `uvm_info(get_full_name(),my_event_pool.get_type_name(),UVM_HIGH); task body(); clk_event = my_event_pool.get("CLOCK EVENT");//this clock event will be triggered and set in the event pool with the same name in some other place where you have the access to the virtual interface handle. . . . clk_event.wait_trigger; . . endtask endclass
You can use the same uvm_event which you have mentioned .
You can get the event with the help of uvm_event_pool, the sharing of
the event happens with respect to the name with which you have set your
clock event.
Please find the code snippet below.
example:class my_sequence extends uvm_sequence; //factory registration //other stuff uvm_event_pool my_event_pool; uvm_event clk_event; . . . clk_event = new(); my_event_pool = uvm_event_pool::get_global_pool(); `uvm_info(get_full_name(),my_event_pool.get_type_name(),UVM_HIGH); task body(); clk_event = my_event_pool.get("CLOCK EVENT");//this clock event will be triggered and set in the event pool with the same name in some other place where you have the access to the virtual interface handle. . . . clk_event.wait_trigger; . . endtask endclass
Better solution is:
Using a uvm_event_pool is not recommended as it results in an
environment that is very co-dependent on other components and isn't
very portable.
Our recommendation it to create an agent which can be used for time/clock advancement. It would have an interface connected to a system clock and have a sequence which would complete when a specified number of clocks have passed.
This technique is recommended since it removes all timing from the HVL testbench and is portable to both simulation and emulation.
-courtesy cgales
Our recommendation it to create an agent which can be used for time/clock advancement. It would have an interface connected to a system clock and have a sequence which would complete when a specified number of clocks have passed.
This technique is recommended since it removes all timing from the HVL testbench and is portable to both simulation and emulation.
-courtesy cgales