There are two kinds of processes in SystemVerilog:static and dynamic.
The SystemVerilog LRM defines a static process as one where "each time the process starts running, there is an end to the process." Another way of putting this is that static processes are created when the code is elaborated and persist until the end of simulation. Static processes come in several forms—each
always,always_comb,always_latch,always_ff and initial procedure is a separate static process as is every concurrent signal assignment.
On the other hand, dynamic processes are created at run-time and execute as independent threads from the processes that spawned them. They can be waited upon or disabled. Dynamic proc-esses come in the form of
fork..join_all,fork..join_none, and dynamic processes created by con-current assertions and cover properties. Dynamic processes allow a testbench to dynamically react to a design under test, control the flow of simulation, build high-level models,and respond to both testbench components and the design.
The SystemVerilog LRM defines a static process as one where "each time the process starts running, there is an end to the process." Another way of putting this is that static processes are created when the code is elaborated and persist until the end of simulation. Static processes come in several forms—each
always,always_comb,always_latch,always_ff and initial procedure is a separate static process as is every concurrent signal assignment.
On the other hand, dynamic processes are created at run-time and execute as independent threads from the processes that spawned them. They can be waited upon or disabled. Dynamic proc-esses come in the form of
fork..join_all,fork..join_none, and dynamic processes created by con-current assertions and cover properties. Dynamic processes allow a testbench to dynamically react to a design under test, control the flow of simulation, build high-level models,and respond to both testbench components and the design.
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