base class - derived class dilemma example

Below example helps to understand parent-child relationship better. many things to look at.

module constraint_test();
        class parent;
          rand int unsigned a;
          constraint c1{
            (a < 10);

          }
        endclass

        class child extends parent;

          rand int unsigned a;
          constraint c2{
            (a > 10);
          }
        endclass

        parent parent_handle = new();
        child child_handle = new();

        initial
        begin
          parent_handle = child_handle;
          parent_handle.randomize();

          $display("a = %d",parent_handle.a);
          $display("a = %d",child_handle.a);
        end

endmodule

case 1:

If there is no handle assignment in above example, first display statement will display value less than 10 and second display statement will display "0", since child_handle.randomize() is not given.  If there is handle assignment, first will display less than 10 and second will display greater than 10. reason is before assignment, 'a' will have different location, after assignment 'a' will point to child class location. so, when parent_handle.randomize() is called, it randomizes child part variables also even though it doesn't have access to child class properties.

case 2:

Assume, no handle assignment in above example, if constraint names are given same in base class and derived class, if you do child_handle.randomize, since constraints are mutually exclusive, it should give error, but instead it wont throw error, it simply dosen't randomize the value and puts default value in it. randomize() function returns 0. If want to throw the error, capture return value of randomize() function. use assert(child_handle.randomize()), it throws error.

case 3:

we can give initial values to variables declared as rand/randc, if we call randomize() function, it overwrites that value.

How to declare and use Nested classes in system verilog

At first instance, I couldn't get how to declare an object of a class which in nested in another class. Below example clears that

*****************************************************************************
module inheritance1;
   class c1;
      static int i = 10;
      int j = 20;
      static int k = 50;

      function void my_print();
         $display("i=%0d",i);
         $display("j=%0d",j);
      endfunction


      class c2;
         int i = 30;
     int j = 40;


     function void my_print(c1 h1);
        $display("i = %0d", i);
        $display("h1.i = %0d", h1.i);
        $display("j = %0d", j);
        $display("h1.j = %0d", h1.j);
        $display("k = %0d", k);
     endfunction
      endclass
   endclass

   c1 o1 = new;
   c1::c2 o2 = new;

   initial
   begin
      o1.my_print();
      o2.my_print(o1);
   end
endmodule

****************************************************************************
output:

 i=10
# j=20
# i = 30
# h1.i = 10
# j = 40
# h1.j = 20
# k = 50
*****************************************************************************

How to Write Action blocks in Assertions

Usual tendency is to write display statements in action blocks(report blocks) to display the error and values. since, the way assertions are executed is a bit different, please go through below example to understand how to write action blocks using $sampled.
***********************************************************************************
This quiz shows a subtle "gotcha" with SystemVerilog Assertions.  The example comes from a real problem encountered at a commpany, though the code has been simplified to focus on the "gotcha" in the assertion.
The assertion verifies that the value of a parity bit is set correctly for the value of data for every clock cycle.  An assertion failure indicates something is wrong with either data or the parity generator logic. 
Assertion Code

property p_parity_check;
  @(posedge clk)
  disable iff (!rstN)  // no checking during active-low reset
  parity == ^data;
endproperty

pcheck: assert property (p_parity_check)
else $error("PARITY ERROR at %0d ns: data = %h, even parity = %b (expected %b)\n",
            $realtime, data, parity, ^data);

This assertion has a subtle "gotcha" when there is an assertion failure.  To illustrate the problem, the design under test for this example always generates a 1 for the parity, which is occasionally an incorrect parity value.  The assertion appears to work most of the time, but sometimes reports an error even though the values printed out in the error message indicate that the data and parity values are correct.  In the following simulation output, the first assertion failure is a real failure, but the second error seems to be incorrect — the value of parity is the right value for the value of data.
Simulation Output

# At 15: Requesting data
# ** Error: PARITY ERROR at 15 ns: data = 00, even parity = 1 (expected 0)
# ** Error: PARITY ERROR at 25 ns: data = 01, even parity = 1 (expected 1)
# At 45: Requesting data
# At 75: Requesting data

Waveform

pcheck             P    F    F    P    P    P    P    P

         +----+    +----+    +----+    +----+    +----+
clk      |    |    |    |    |    |    |    |    |    |
     ----+    +----+    +----+    +----+    +----+    +----

     +        +--------------------------------------------
RSTn |        |
     +--------+

     ------------------------+-------------------+---------
data    00 (hex)             | 01 (hex)          | 02 (hex)
     ------------------------+-------------------+---------

              +--------------------------------------------
parity        |
     ---------+

Why did the assertion show a second failure when the printed values are correct at that time?

Answer

The "gotcha" in this assertion has to do with the order in which simulators evaluate assertions, print messages, and change design signal values.  The IEEE SystemVerilog defines a specific order for processing events on a clock edge.

1. Any signals to be evaluated by a concurrent assertion are "sampled" in a "Preponed event region" of a clock edge.  This is a stable point, before any signal changes that might occur as a result of the clock edge have been processed.
2. Next, design modules process signal changes in the "Active event region" and the "NBA Update event region".
3. After the design changes for that clock edge are processed, assertions error messages are printed in a "Reactive event region".

This delta between sampling values and the assertion results from processing those values represents register-based hardware clock-to-Q behavior, and is as it should be.  It does mean, however, that, by the time the pass/fail statements are executed, RTL code can, and probably will, be changing signal values due to the clock edge.
In the assertion in the example above, it appears that the second failure message should not have happened -- the value or parity appears to be correct, and yet the assertion failed.  The real problem, though, is that the assertion error message is showing the value of data after the assertion has sampled data.  The sampled value wass not the same as the printed value.  The assertion failure was correct, but the error message was misleading.  Gotcha!.
SVA has a simple solution for this "gotcha".  If a pass/fail statement needs to print the values of signals that are used by the assertion, then the message should print the Preponed value — the same value used by the assertion — by using the $sampled() function.  $sampled() returns the Preponed value of a signal for the current moment in simulation time.  the correctly written assertion for this example is:

property p_parity_check;
  @(posedge clk)
  disable iff (!rstN)  // no checking during active-low reset
  parity == ^data;
endproperty

pcheck: assert property (p_parity_check)
else $error("PARITY ERROR at %0d ns: data = %h, even parity = %b (expected %b)\n",
            $realtime, $sampled(data), $sampled(parity), ^($sampled(data))); 

******************************************************************************************** 

Blogs I follow

List of Blogs:

Blogs

Arasan company:    http://arasan.com/company/blog/

http://analytical-verification.blogspot.in/2014/04/deciphering-uvm-1.html

http://cluelogic.com/2011/05/customizing-ovm-message-format/#more-85 ( must see everyday)

http://www.verilab.com/blog/

http://www.agilesoc.com/

http://blogs.mentor.com/verificationhorizons/

http://whatisverification.blogspot.in/

Below are list of links from Suthrland website: ( some of them are good to follow)

FAQ's and Information

The official IEEE 1364 Verilog Standards Group Page Information on the IEEE-1364 Verilog standard.
SystemVerilog Information Page Information on the Accellera extensions to the Verilog-2001 standard.
comp.lang.verilog news group FAQ A hyperlinked version of the Frequently Asked Questions collected on the Verilog news group bulletin board. The information is a bit out of date, but still useful.
EDA Cafe A general resource on Design Automation. Lots of useful links and other Verilog related information, including links to free and demo versions of EDA software.
eECAD A software "rental" portal. Most major simulators, synthesis tools and other EDA tools are available for rent on a per-use or per-hour basis.
Verilog.Net An independent Verilog resource page, with links to many Verilog related web sites, and a list of major EDA vendors.
Chris Spear's SystemVerilog Verification and Verilog PLI Web Page
Rajesh Bawankule's Verilog Page Verilog FAQ's and reference. BEWARE! This site is full of those awful pop-up ads :(
VeriPool Public Domain Verilog Resources Links to various Verilog resources and software, including Perl scripts.
Project VeriPage a site deditcated to the Verilog PLI. BEWARE! This site is full of those awful pop-up ads :(
Free Model Foundry A resource for Verilog models and model development.

http://www.systemverilog.in/direct-programming-interface.php  Good link to learn DPI calls in Systemverilog in complete.

Assertions instead of FSM's/logic for scoreboarding or verification:

https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3/Assertions-Instead-of-FSMs/logic-for-Scoreboarding-and-Verification

User Groups and Conferences

Accellera A user organization to promote the use of hardware description languages such as Verilog and VHDL and encourage advancements in hardware language and design methodologies.
Deep Chip John Cooley's ESNUG Articles (Electronic Synopsys Users Group).
Verification Guild Janick Bergeron's forum where verification professionals can discuss any issues and challenges.
DVCon Conference Design and Verification Conference (formerly International HDL Conference and before that International Verilog Conference or IVC). Specialized trade show and technical conference for Verilog and VHDL products. Held annually in Santa Clara, California around March or April.
DAC Conference Design Automation Conference. The premier trade show for Electronic Design Automation. Held annually in different locations in the US around June.
DesignCon Conference Design Conference. product technologies, design methodologies, and EDA software, with a focus on system-on-chip design. Held annually in in San Jose, around February.
ICCAD Conference The International Conference on Computer Aided Design. Held annually in different locations in the US around November.
Synopsys User's Group (SNUG) A very technical conference on synthesis using Synopsys tools. Held twice each year: In Santa Jose, California around March, and in Boston, Massachusetts around September.
Verilog-AMS Web page by the Verilog Analog Mixed-Signal standard group.
EE Times Calendar of Tradeshows and Conferences

Free HDL Tutorials

On-line Verilog Primer A short on-line Verilog Course.
On-line Verilog tutorial 1-day on-line Verilog Course courtesy of Deepak Kumar Tala.
PDF Verilog tutorial A 123 page tutorial on Verilog courtesy of Deepak Kumar Tala (a large file with lots of graphics).
PDF Verilog tutorial A 30-page Verilog tutorial with synthesis guidelines.

HDL Editors

Emacs editor Verilog mode Michael McNamara's Verilog mode for Emacs editors is available here.
Nedit for Unix A freeware ($30) programming editor for most Unix operating systems, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text.
Ultra Edit for PC's A shareware ($30) programming editor for windows-based PC's, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text. Be sure to download the Verilog "wordfile" in addition to the editor.

EDA Vendor Guides

D&R Web Page A directory of Design Reuse vendors and resources
EDA "Freeware" pages Links to various freeware EDA tools, and home page for V-2000, a freeware Verilog, VHDL and Analog Mixed Signal project, distributed under a GNU license agreement.
EDAtoolsCafe A sponsored web site with news about EDA and IC companies, with lots of links and information. All material on the site is sponsored by advertisers, so beware of biased information.

Commercial Logic Simulators

(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)
Cadence Design Systems Inc. NC-Verilog and Verilog-XL (the original Verilog simulator, developed by Gateway Design Automation in 1984)
Fintronic USA, Inc. Super FinSim
Mentor Graphics Corp. ModelSim (formerly from Model Technology) mixed Verilog, SystemVerilog and VHDL simulator.
Simucad, Inc. Silos III
SynaptiCad, Inc. VeriLogger Pro
Synopsys, Inc. VCS Verilog and SystemVerilog simulator (originally developed by Chronologic, then owned by Viewlogic)
TJ Systems V2Sim mixed Verilog, SystemVerilog and VHDL simulator)

Freeware Simulators

(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)
"Icarus" Icarus Verilog, a popular freeware Verilog simulator. What happened to the popular VeriWell simulator from Wellspring? Wellspring is no longer in business, but the popular VeriWell simulator lives on as the core to the VeriLogger Pro simulator from SynaptiCad, Inc. A demo version of Verilogger Pro can be downloaded, which gives similar capabilities to the ones that so many budget-tight college students appreciated about the VeriWell simulator.

Synthesis Tools

(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)
Cadence Design Systems Inc. Encounter RTL Compiler and BuildGates (formerly from Ambit)
Mentor Graphics Corp. Precision Synthesis and Leonardo Spectrum (formerly from Exemplar)
Synopsys, Inc. Design Compiler
Synplicity, Inc. Synplify and Amplify

Electronic Design Magazines

EE Times online Magazine
EEdesign online Magazine


Follow on AgnySys free tool to create SV/UVM code in below link. This tool will be released in DAC and is free.....

http://www.agnisys.com/dvi/
http://eecatalog.com/chipdesign/2014/05/09/speed-design-verification-by-developing-cleaner-svuvm-code/

Parameterized classes, how does they effect static members in it and about Factory Macros

Below information is copied from Mentor Graphics blog. Keeping it in my blog for my reference.

Below is the original link of topic.

http://blogs.mentor.com/verificationhorizons/blog/2011/02/13/parameterized-classes-static-members-and-the-factory-macros/

*********************************************************************************

When you declare a parameterized class, it is more like a template, or generic class than a real class type. Only specializations of parameterized classes are real types. Suppose I have the two class definitions in the table below:

Un-parameterized	Parameterized
class A;   static string name = “packet”; endclass	class B #(int w=1);   static string name = “packet”; endclass

The class A definition by itself creates the static variable A::name initialized with the string “packet” without any other reference to class A. As soon as you add parameters to a class definition, like the parameter w in class B, the class becomes a generic class and the static variable name does not get created. As soon as there are specializations of the class B, each unique specialization causes the static variables inside the class to be instantiated.  The following statements create two specializations of class B and two instances of the static variable.  B#(2)::name and B#(3)::name are both set to “packet”.

typedef B#(2) B2; B#(3) B3_1h; B#(3) B3_2h;

The two class variable declarations (B3_1h and B3_2h) represent only one unique specialization of B because its parameters have the same value in both declarations. The variable B#(1)::name does not exist unless there is some other reference to B or B#(1) somewhere else.
What if you wanted the static string variable name to have a different value for each unique specialization of B? You could write something like

class B #(int w=1);   static string name = $psprintf(“packet%0d”,w); endclass

Now assuming the previous typedef and variable declarations above, B#(2)::name would have the value “packet2” and B#(3)::name would have the value “packet3”. There would be no instance B#(1)::name and the string “packet1” would never have been generated.

Below gives, complete example of static variable in param class.

_______________________________________________________________________________
module static_in_param_class();

    class A#(int w = 1);

        static string name = "packet";
   
    endclass

    initial
    begin

    A#(2) A1;
//    $display("Value of static variable is %s", A::name);  // Valid only for un-parameterized class. If class A has no parameters, this works.
    $display("Value of static variable is %s", A1.name);  // If class A has parameters as shown, It will be generic class, we need to create a handle with specific parameter and can access the static member only with handle.

    end

endmodule
_________________________________________________________________________________


Now let us go back to the `ovm_object_utils macro. Suppose we have the following class definition

`include “ovm_macros.svh” import ovm_pkg::*; class packetA extends ovm_object; `ovm_object_utils(packetA) … endclass

Looking at just the factory registration statement this macro inserts for us (this little one line macro expands to over 100 lines of code just to support the field automation macros), we see a typedef for a specialization of the parameterized class ovm_object_registry called type_id.

import ovm_pkg::*; class packetA extends ovm_object;   typedef ovm_object_registry#(packetA,”packetA”) type_id;  static function type_id get_type();     return type_id::get();   endfunction   … endclass

The specialized class type_id gives us access to all the static declarations inside ovm_object_registry. The code inside that class does something similar to what class A did above, except that it builds a global list of all string names and their associated types that can be used by the factory. The OVM gives you the choice of using the string name “packet” or the static function packetA::get_type() to set overrides, depending on which factory methods you use. The problem using the string names is that there is no type checking until run-time when the override statements are executed. We prefer you use type references to perform overrides
packetA::type_id::set_inst_override(extended_packetA::get_type(),”env.my_agent.*”);
Finally, let us take a look at a parameterized class, but assume we used the same `ovm_object_utils macro.

import ovm_pkg::*; class packetB #(int w=1) extends ovm_object;   typedef ovm_object_registry#(packetB#(w),”packetB#(w)”) type_id;  static function type_id get_type();     return type_id::get();   endfunction   … endclass

There are two problems here. The first is that this is now a generic class. The string “packetB#(w)” will not put on the factory registration list unless there is a specialization of the class packetB somewhere. The second is that if there are more than one specializations of packetB, they all will be registered with the same string name, producing an error at run time.
The `ovm_object_param_utils macro simply leaves the second parameter to ovm_object_registry as the null string and forces you to use type references for your overrides. These type references also create the specializations needed to create the static methods inside these classes.
packetB#(2)::type_id::set_inst_override(
  extended_packetB#(2)::get_type(),”env.my_agent.*”);
The references to packetB#(2) and extended_packetB#(2) are checked at compile time and cause the static methods within these references to be created.
You can use $psprintf to register a string name as long as the string is unique for each specialization of the class. This can be difficult when the parameters are types.

import ovm_pkg::*; class packetB #(int w=1) extends ovm_object;   parameter sting name = $psprintf(“packetB%0d”,w);   typedef ovm_object_registry#(packetB#(w),name) type_id;…

OK, I’m done. If you still need more background information. I recommend another DVCon09 paper I wrote with Adam about Using Parameterized and Factories.

***********************************************************************************