How to declare and use Nested classes in system verilog

At first instance, I couldn't get how to declare an object of a class which in nested in another class. Below example clears that

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module inheritance1;
   class c1;
      static int i = 10;
      int j = 20;
      static int k = 50;

      function void my_print();
         $display("i=%0d",i);
         $display("j=%0d",j);
      endfunction


      class c2;
         int i = 30;
     int j = 40;


     function void my_print(c1 h1);
        $display("i = %0d", i);
        $display("h1.i = %0d", h1.i);
        $display("j = %0d", j);
        $display("h1.j = %0d", h1.j);
        $display("k = %0d", k);
     endfunction
      endclass
   endclass

   c1 o1 = new;
   c1::c2 o2 = new;

   initial
   begin
      o1.my_print();
      o2.my_print(o1);
   end
endmodule

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output:

 i=10
# j=20
# i = 30
# h1.i = 10
# j = 40
# h1.j = 20
# k = 50
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