List of Blogs:
http://analytical-verification.blogspot.in/2014/04/deciphering-uvm-1.html
http://cluelogic.com/2011/05/customizing-ovm-message-format/#more-85 ( must see everyday)
http://www.verilab.com/blog/
http://www.agilesoc.com/
http://blogs.mentor.com/verificationhorizons/
http://whatisverification.blogspot.in/
Below are list of links from Suthrland website: ( some of them are good to follow)
SystemVerilog Information Page Information on the Accellera extensions to the Verilog-2001 standard.
comp.lang.verilog news group FAQ A hyperlinked version of the Frequently Asked Questions collected on the Verilog news group bulletin board. The information is a bit out of date, but still useful.
EDA Cafe A general resource on Design Automation. Lots of useful links and other Verilog related information, including links to free and demo versions of EDA software.
eECAD A software "rental" portal. Most major simulators, synthesis tools and other EDA tools are available for rent on a per-use or per-hour basis.
Verilog.Net An independent Verilog resource page, with links to many Verilog related web sites, and a list of major EDA vendors.
Chris Spear's SystemVerilog Verification and Verilog PLI Web Page
Rajesh Bawankule's Verilog Page Verilog FAQ's and reference. BEWARE! This site is full of those awful pop-up ads :(
VeriPool Public Domain Verilog Resources Links to various Verilog resources and software, including Perl scripts.
Project VeriPage a site deditcated to the Verilog PLI. BEWARE! This site is full of those awful pop-up ads :(
Free Model Foundry A resource for Verilog models and model development.
http://www.systemverilog.in/direct-programming-interface.php Good link to learn DPI calls in Systemverilog in complete.
Assertions instead of FSM's/logic for scoreboarding or verification:
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3/Assertions-Instead-of-FSMs/logic-for-Scoreboarding-and-Verification
Deep Chip John Cooley's ESNUG Articles (Electronic Synopsys Users Group).
Verification Guild Janick Bergeron's forum where verification professionals can discuss any issues and challenges.
DVCon Conference Design and Verification Conference (formerly International HDL Conference and before that International Verilog Conference or IVC). Specialized trade show and technical conference for Verilog and VHDL products. Held annually in Santa Clara, California around March or April.
DAC Conference Design Automation Conference. The premier trade show for Electronic Design Automation. Held annually in different locations in the US around June.
DesignCon Conference Design Conference. product technologies, design methodologies, and EDA software, with a focus on system-on-chip design. Held annually in in San Jose, around February.
ICCAD Conference The International Conference on Computer Aided Design. Held annually in different locations in the US around November.
Synopsys User's Group (SNUG) A very technical conference on synthesis using Synopsys tools. Held twice each year: In Santa Jose, California around March, and in Boston, Massachusetts around September.
Verilog-AMS Web page by the Verilog Analog Mixed-Signal standard group.
EE Times Calendar of Tradeshows and Conferences
On-line Verilog tutorial 1-day on-line Verilog Course courtesy of Deepak Kumar Tala.
PDF Verilog tutorial A 123 page tutorial on Verilog courtesy of Deepak Kumar Tala (a large file with lots of graphics).
PDF Verilog tutorial A 30-page Verilog tutorial with synthesis guidelines.
Nedit for Unix A freeware ($30) programming editor for most Unix operating systems, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text.
Ultra Edit for PC's A shareware ($30) programming editor for windows-based PC's, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text. Be sure to download the Verilog "wordfile" in addition to the editor.
EDA "Freeware" pages Links to various freeware EDA tools, and home page for V-2000, a freeware Verilog, VHDL and Analog Mixed Signal project, distributed under a GNU license agreement.
EDAtoolsCafe A sponsored web site with news about EDA and IC companies, with lots of links and information. All material on the site is sponsored by advertisers, so beware of biased information.
Cadence Design Systems Inc. NC-Verilog and Verilog-XL (the original Verilog simulator, developed by Gateway Design Automation in 1984)
Fintronic USA, Inc. Super FinSim
Mentor Graphics Corp. ModelSim (formerly from Model Technology) mixed Verilog, SystemVerilog and VHDL simulator.
Simucad, Inc. Silos III
SynaptiCad, Inc. VeriLogger Pro
Synopsys, Inc. VCS Verilog and SystemVerilog simulator (originally developed by Chronologic, then owned by Viewlogic)
TJ Systems V2Sim mixed Verilog, SystemVerilog and VHDL simulator)
"Icarus" Icarus Verilog, a popular freeware Verilog simulator. What happened to the popular VeriWell simulator from Wellspring? Wellspring is no longer in business, but the popular VeriWell simulator lives on as the core to the VeriLogger Pro simulator from SynaptiCad, Inc. A demo version of Verilogger Pro can be downloaded, which gives similar capabilities to the ones that so many budget-tight college students appreciated about the VeriWell simulator.
Cadence Design Systems Inc. Encounter RTL Compiler and BuildGates (formerly from Ambit)
Mentor Graphics Corp. Precision Synthesis and Leonardo Spectrum (formerly from Exemplar)
Synopsys, Inc. Design Compiler
Synplicity, Inc. Synplify and Amplify
EEdesign online Magazine
Follow on AgnySys free tool to create SV/UVM code in below link. This tool will be released in DAC and is free.....
http://www.agnisys.com/dvi/
http://eecatalog.com/chipdesign/2014/05/09/speed-design-verification-by-developing-cleaner-svuvm-code/
Blogs
Arasan company: http://arasan.com/company/blog/http://analytical-verification.blogspot.in/2014/04/deciphering-uvm-1.html
http://cluelogic.com/2011/05/customizing-ovm-message-format/#more-85 ( must see everyday)
http://www.verilab.com/blog/
http://www.agilesoc.com/
http://blogs.mentor.com/verificationhorizons/
http://whatisverification.blogspot.in/
Below are list of links from Suthrland website: ( some of them are good to follow)
FAQ's and Information
The official IEEE 1364 Verilog Standards Group Page Information on the IEEE-1364 Verilog standard.SystemVerilog Information Page Information on the Accellera extensions to the Verilog-2001 standard.
comp.lang.verilog news group FAQ A hyperlinked version of the Frequently Asked Questions collected on the Verilog news group bulletin board. The information is a bit out of date, but still useful.
EDA Cafe A general resource on Design Automation. Lots of useful links and other Verilog related information, including links to free and demo versions of EDA software.
eECAD A software "rental" portal. Most major simulators, synthesis tools and other EDA tools are available for rent on a per-use or per-hour basis.
Verilog.Net An independent Verilog resource page, with links to many Verilog related web sites, and a list of major EDA vendors.
Chris Spear's SystemVerilog Verification and Verilog PLI Web Page
Rajesh Bawankule's Verilog Page Verilog FAQ's and reference. BEWARE! This site is full of those awful pop-up ads :(
VeriPool Public Domain Verilog Resources Links to various Verilog resources and software, including Perl scripts.
Project VeriPage a site deditcated to the Verilog PLI. BEWARE! This site is full of those awful pop-up ads :(
Free Model Foundry A resource for Verilog models and model development.
http://www.systemverilog.in/direct-programming-interface.php Good link to learn DPI calls in Systemverilog in complete.
Assertions instead of FSM's/logic for scoreboarding or verification:
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3/Assertions-Instead-of-FSMs/logic-for-Scoreboarding-and-Verification
User Groups and Conferences
Accellera A user organization to promote the use of hardware description languages such as Verilog and VHDL and encourage advancements in hardware language and design methodologies.Deep Chip John Cooley's ESNUG Articles (Electronic Synopsys Users Group).
Verification Guild Janick Bergeron's forum where verification professionals can discuss any issues and challenges.
DVCon Conference Design and Verification Conference (formerly International HDL Conference and before that International Verilog Conference or IVC). Specialized trade show and technical conference for Verilog and VHDL products. Held annually in Santa Clara, California around March or April.
DAC Conference Design Automation Conference. The premier trade show for Electronic Design Automation. Held annually in different locations in the US around June.
DesignCon Conference Design Conference. product technologies, design methodologies, and EDA software, with a focus on system-on-chip design. Held annually in in San Jose, around February.
ICCAD Conference The International Conference on Computer Aided Design. Held annually in different locations in the US around November.
Synopsys User's Group (SNUG) A very technical conference on synthesis using Synopsys tools. Held twice each year: In Santa Jose, California around March, and in Boston, Massachusetts around September.
Verilog-AMS Web page by the Verilog Analog Mixed-Signal standard group.
EE Times Calendar of Tradeshows and Conferences
Free HDL Tutorials
On-line Verilog Primer A short on-line Verilog Course.On-line Verilog tutorial 1-day on-line Verilog Course courtesy of Deepak Kumar Tala.
PDF Verilog tutorial A 123 page tutorial on Verilog courtesy of Deepak Kumar Tala (a large file with lots of graphics).
PDF Verilog tutorial A 30-page Verilog tutorial with synthesis guidelines.
HDL Editors
Emacs editor Verilog mode Michael McNamara's Verilog mode for Emacs editors is available here.Nedit for Unix A freeware ($30) programming editor for most Unix operating systems, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text.
Ultra Edit for PC's A shareware ($30) programming editor for windows-based PC's, with keyword highlighting for Verilog, VHDL, C and many other languages. This editor has many very handy features, including editing columns of text. Be sure to download the Verilog "wordfile" in addition to the editor.
EDA Vendor Guides
D&R Web Page A directory of Design Reuse vendors and resourcesEDA "Freeware" pages Links to various freeware EDA tools, and home page for V-2000, a freeware Verilog, VHDL and Analog Mixed Signal project, distributed under a GNU license agreement.
EDAtoolsCafe A sponsored web site with news about EDA and IC companies, with lots of links and information. All material on the site is sponsored by advertisers, so beware of biased information.
Commercial Logic Simulators
(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)Cadence Design Systems Inc. NC-Verilog and Verilog-XL (the original Verilog simulator, developed by Gateway Design Automation in 1984)
Fintronic USA, Inc. Super FinSim
Mentor Graphics Corp. ModelSim (formerly from Model Technology) mixed Verilog, SystemVerilog and VHDL simulator.
Simucad, Inc. Silos III
SynaptiCad, Inc. VeriLogger Pro
Synopsys, Inc. VCS Verilog and SystemVerilog simulator (originally developed by Chronologic, then owned by Viewlogic)
TJ Systems V2Sim mixed Verilog, SystemVerilog and VHDL simulator)
Freeware Simulators
(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)"Icarus" Icarus Verilog, a popular freeware Verilog simulator. What happened to the popular VeriWell simulator from Wellspring? Wellspring is no longer in business, but the popular VeriWell simulator lives on as the core to the VeriLogger Pro simulator from SynaptiCad, Inc. A demo version of Verilogger Pro can be downloaded, which gives similar capabilities to the ones that so many budget-tight college students appreciated about the VeriWell simulator.
Synthesis Tools
(Note: this is only a partial list. New products may have been introduced since this list was compiled, and products in this list may no longer be available, have changed product names, and/or have been acquired by another company)Cadence Design Systems Inc. Encounter RTL Compiler and BuildGates (formerly from Ambit)
Mentor Graphics Corp. Precision Synthesis and Leonardo Spectrum (formerly from Exemplar)
Synopsys, Inc. Design Compiler
Synplicity, Inc. Synplify and Amplify
Electronic Design Magazines
EE Times online MagazineEEdesign online Magazine
Follow on AgnySys free tool to create SV/UVM code in below link. This tool will be released in DAC and is free.....
http://www.agnisys.com/dvi/
http://eecatalog.com/chipdesign/2014/05/09/speed-design-verification-by-developing-cleaner-svuvm-code/
super ra mama...
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